In a case where, for example, AD conversion is performed within a limited area such as a pixel by utilizing a signal reading-out system of a solid-state imaging apparatus, the best area efficiency system is an integral type (slope type) AD conversion system which includes a comparator and a digital circuit in a subsequent stage of the comparator.
NPL 1 is proposed as a technology with which AD conversion is tried to be realized within a limited area by using the integral type AD conversion system. For example, the system of NPL 1 adopts a circuit configuration in which a slope signal is inputted to a comparator a plurality of times with a digital circuit in a subsequent stage as one DRAM circuit. For example, in the case of 8-bit AD conversion, the same slope signal is repetitively inputted to the comparator eight times. Then, an operation for storing a code of 0 or 1 at a time point at which an output from the comparator is inverted in a DRAM, and an operation for outputting the code of interest are repetitively performed eight times. At a time point at which comparison is ended with respect to an entire surface, the code of interest is read out to the outside.